The present invention relates to latency uncertainty reduction.
FIG. 1 is a block diagram of a system with latency uncertainty. In FIG. 1, system 100, includes receiver 110, word aligner 120, user logic 130, phase crossing first-in-first-out (FIFO) 150, and transmitter 160. A receiver and a transmitter may herein be designated as RX and TX, respectively. The combination of a receiver and a transmitter may herein be referred to as a transceiver. In addition to referring to a combination of a receiver and a transmitter, a transceiver may also herein be used to refer to a receiver or a transmitter. As system 100 includes a transceiver, it may herein be referred to as a transceiver system. System 100 may also herein be referred to as a device, more specifically a transceiver device, i.e., a device that includes a transceiver. The terms transceiver system and transceiver device (in addition to being used to refer to a system or device having a transceiver) may also herein be used to refer to a transceiver.
System 100 may be a programmable logic device (PLD). However, system 100 is not limited to being a PLD, but may be any circuit or device. In the example of system 100, word aligner 120, user logic 130, and phase crossing FIFO 150 are part of the PLD core, which may also be referred to as the PLD fabric.
Receiver 110 includes input interface (I/F) 111, clock data recovery (CDR) unit 112, deserializer 113 which converts serial data to parallel data, and divider 116. Deserializer 113 includes serial register 114 operating with a serial clock and a parallel register 115 operating with a parallel clock, which may also herein be referred to as a recovered clock or a receiver parallel clock. CDR unit 112 receives input data and recovers a serial input clock therefrom. CDR unit 112 provides the input data to deserializer 113 and the serial input clock to divider 116. Divider 116 is an N divider that divides the serial input clock by N to provide the receiver parallel clock, where N is an integer that represents the number of bits per cycle of the receiver parallel clock and may herein be referred to as the deserialization factor. In one example, N is equal to 10, but may be equal to any integer greater than 1.
Divider 116 can produce a recovered clock that has any of N phases. FIG. 2 illustrates different phases of the recovered clock relative to the serial clock and serial incoming data stream of FIG. 1. In FIG. 2, the serial incoming data stream and serial clock are respectively represented by signals 210 and 220. Similarly, parallel clocks with phases 0, 1, 2, 3, 4, and 9 are respectively represented by signals 230, 231, 232, 233, 234, and 239. In FIG. 2, N is assumed to be 10, and therefore, there are 10 different phases of the recovered clock, which are numbered phases 0 through 9. These 10 phases produce 10 different word orderings out of deserializer 113. In the example of FIG. 2, phase 0 produces 10-bit parallel words which at cycle 0 include bits D9, D8, D7, D6, D5, D4, D3, D2, D1, and D0 and at cycle 1 include bits D19, D18, D17, D16, D15, D14, D13, D12, D1, and D10; phase 1 produces 10-bit parallel words which at cycle 0 include bits D0,X,X,X,X,X,X,X,X. and X (where X indicates a do not care bit) and at cycle 1 include bits D10, D9, D8, D7, D6, D5, D4, D3, D2, and D1; phase 2 produces 10-bit parallel words which at cycle 0 include bits D1, D0, X, X, X, X, X, X, X, and X and at cycle 1 include bits D11, D10, D9, D8, D7, D6, D5, D4, D3, and D2; and phase 9 produces 10-bit parallel words which at cycle 0 include bits D8, D7, D6, D5, D4, D3, D2, D1, D0, and X and at cycle 1 include bits D18, D17, D16, D15, D14, D13, D12, D11, D10, and D9. It is to be noted that for each of phases 0 to 9, cycle 0 is the first cycle which includes bit D0 and cycle 1 is the cycle immediately after cycle 0.
Referring back to FIG. 1, word aligner 120 receives parallel words from receiver 110 and aligns the parallel words to a desired word boundary. Word aligner 120 also receives the recovered clock. In the example of FIG. 1, word aligner 120 is implemented in the programmable logic fabric of the PLD. The word alignment performed by word aligner 120 is needed in situations where user designs operate on the parallel data expecting certain predefined words (e.g., comma characters like K28.5). In such situations, user logic 130 would properly process the parallel data only when it is aligned to a desired word boundary. The process of word alignment to the desired word introduces a Deserializer/Word aligner latency uncertainty. For example, if the desired predefined word was in fact “D9-D0”, then in the phase 0 case, no alignment is needed; in the phase 1 case, an alignment of 1 bits is needed, which introduces an uncertainty of 1 bit period or unit internal (UI); in the phase 2 case, an alignment of 2 bits is needed, which introduces an uncertainty of 2 bit periods; and in the phase 9 case, an alignment of 9 bits is needed, which introduces an uncertainty of 9 bit periods. Thus, the word alignment process introduces a bit level uncertainty of up to N−1 bit periods, where N is the deserialization factor.
User logic 130 receives aligned words from word aligner 120 and the recovered clock from receiver 110. User logic 130 processes the aligned words and provides the processed data to phase crossing FIFO 150, which also receives the recovered clock from receiver 110 and a transmitter parallel clock from transmitter 160. Phase crossing FIFO 150 receives data on the recovered clock and outputs data on the transmitter parallel clock. The recovered clock and the transmitter parallel clock have the same frequency, but an unknown phase difference. As a result, there is an uncertainty of one clock cycle between the recovered clock and the transmitter parallel clock. This is described in further detail below.
Transmitter 160 includes output I/F 161, serializer 163 which converts parallel data to serial data, divider 166 (which may herein be referred to as transmitter divider 166), and phase locked loop (PLL) 170 (which may herein be referred to as transmitter PLL 170). Serializer 163 includes serial register 164 operating on a serial output clock and a parallel register 165 operating on the transmitter parallel clock, which may also herein be referred to as a parallel transmitter clock or parallel output clock. Divider 166 is an N divider that divides the serial output clock by N to provide the transmitter parallel clock, where N is as defined above. PLL 170 includes phase frequency detector (PFD) 172, voltage controlled oscillator (VCO) 174, and divider 176 connected as shown in FIG. 1. As can be seen in FIG. 1, divider 176 (an M divider) is a feedback path divider that divides the output of VCO 174 by a factor of M, where M is an integer representing the ratio between the frequency of the signal output by VCO 174 and the frequency of the recovered clock received by PFD 172. PLL 170 receives the recovered clock as a reference signal and outputs a serial output clock signal whose frequency is M times that of the recovered clock signal. PFD 172 ensures that both clock signals that it receives (recovered clock signal and the output of divider 176) have the same frequency and are in phase with each other by making VCO 174 increase or decrease the frequency of its output as necessary. In the example shown in FIG. 1, M is equal to N and therefore, the serial output clock signal has a frequency that is N times that of the recovered clock signal. In other words, the serial output clock signal has a frequency that is equal to the serial input clock frequency. Divider 166, which is an N divider, divides the serial output clock signal by N to produce the transmitter parallel clock signal. Thus, the transmitter parallel clock signal has the same frequency as the recovered clock signal.
Table 1 below illustrates the relation between the serial data rate and latency uncertainty for a system such as system 100, in a case where N is equal to 10.
TABLE 1SerialParallelDeserializer/WordRX/TXData RateClockAligner LatencyTransfer(in megaFrequencyUncertaintyLatencyTotalbits per(in mega(0.9 cycle)UncertaintyLatencysecondHz(in nano seconds(1 cycle)Uncertainty(Mbps))(MHz))(ns))(in ns)(in ns)61461.414.6516.2830.931228122.87.328.1415.462456245.63.664.077.73
In Table 1, serial data rates of 614 Mbps (mega bits per second), 1228 Mbps, and 2456 Mbps are chosen as examples. As can be seen in Table 1, system 100 involves both a deserializer/word aligner latency uncertainty (which may herein be referred to as a word aligner latency uncertainty), a receiver/transmitter transfer latency uncertainty (which may herein be referred to as receiver-to-transmitter transfer latency uncertainty or transfer latency uncertainty), and a total latency uncertainty that is the sum of the word aligner latency uncertainty and the transfer latency uncertainty.
Certain protocols mandate a bit-level latency uncertainty that is in the order of nanoseconds. One such protocol is the Common Public Radio Interface (CPRI) protocol which mandates a maximum bit-level latency uncertainty of 16.3 ns across a serial link. Thus, in some cases, it is desirable to reduce the latency uncertainty of a system.